Question (1)
A simple SR-Latch
using two NOR gates
The diagram above shows a simple latch
and typical pulsed waveforms that are used to control its state.
If a logic 1 is applied to the RESET
input while a logic 0 is applied to the set input, then because of the NOR gate
truth table, output Q will be forced to a logic 0.
[For
a NOR gate, any input at 1 causes the output to be at 0]
·
Since
the Q output is at 0 and the S input is also at 0 then the Q’ output is at 1.
·
This
is the RESET state of the circuit in which Q=0 and Q’ =1.
·
If
now a logic 1 is applied to the SET input while a logic 0 is applied to the
RESET input, then because of the NOR gate truth table, output Q’ will be forced
to a logic 0.
[For
a NOR gate, any input at 1 causes the output to be at 0.]
·
Since
the Q’ output is at 0 and the R input is also at 0 then the Q output goes to 1.
·
This
is the SET state of the circuit in which Q=1 and Q’=0.
·
Note
that it is not allowed to both SET and RESET the latch at the same time. ( S=1
and R=1 simultaneously. If this condition is applied and then removed, we
cannot be sure of the final state of the circuit.
Truth
table for the SR latch constructed using NOR gates
An SR latch constructed using two NAND gates
The diagram above shows a NAND gate
latch and typical pulsed waveforms that are used to control its state.
If a logic 0 is applied to the RESET
input while a logic 1 is applied to the set input, then because of the NAND
gate truth table, output Q’ will be forced to a logic 1.
[For
a NAND gate, any input at 0 causes the output to be at 1.]
·
Since
the Q’ output is at 1 and the S input is also at 1 then the Q output is at 0.
·
This
is the RESET tate of the circuit in which Q=0 and Q’ =1.
·
If
now a logic 0 is applied to the SET input while a logic 1 is applied to the
RESET input, then because of the NAND gate truth table, output Q will be forced
to a logic 1.
·
Since
the Q output is at 1 and the R input is also at 1 then the Q’ output goes to 0.
·
This
is the SET state of the circuit in which Q=1 and Q’=0.
As
for the NOR gate version note that it is not allowed to both SET and RESET the
flip flop at the same time. (S=0 and R=0 simultaneously. If this condition is
applied and then removed, we cannot be sure of the final state of the circuit.
Truth
table for the latch constructed using NAND gates
A
simple clocked latch
We can convert the simple flip-flops
above into timed (clocked devices) by adding some input gating. If we start
with the NOR latch block diagram we need only add two AND gates as shown below:
When the Enable input "EN"
is at logic level "0", the outputs of the two AND gates are at logic
level "0", (AND Gate principles) regardless of the two inputs S and
R, latching the two outputs Q and Q into their last known states. When the
enable input "EN" changes to logic level "1" the circuit
responds as a normal SR bistable flip-flop and the two AND gates become
transparent. This enable input can also be connected to a clock signal adding
clock synchronization to the flip-flop creating a "clocked SR
flip-flop".
Question (2)
S-R
Latch
A
bistable multivibrator has two stable states, as indicated by the prefix bi in
its name. Typically, one state is referred to as set and the other as reset.
The simplest bistable device, therefore, is known as a set-reset, or S-R,
latch.
Gated
S-R Latch
The
Gated SR Latch is an electronic component with a one-bit memory. When setting
or resetting the latch, it keep its value at the output ports when the 'S' and
'R' inputs are low. The gated SR Latch is only transparent if you make the
input 'C' high. When you make both 'S' and 'R' active, then the output level is
not defined.
D
Latch
One
very useful variation on the SR latch circuit is the Data latch, or D latch as
it is generally called. Since the enable input on a gated S-R latch provides a
way to latch the Q and not-Q outputs without regard to the status of S or R, we
can eliminate one of those inputs to create a multivibrator latch circuit with
no "illegal" input states. Such a circuit is called a D latch
Edge-Triggered
Latch
In
many digital applications, however, it is desirable to limit the responsiveness
of a latch circuit to a very short period of time instead of the entire
duration that the enabling input is activated. One method of enabling a
multivibrator circuit is called edge triggering, where the circuit's data
inputs have control only during the time that the enable input is transitioning
from one state to another.
J-K
flip flop
The
JK flip flop is the most versatile flip-flop, and the most commonly used flip
flop when discrete devices are used to implement arbitrary state machines. Like
the RS flip-flop, it has two data inputs, J and K, and a clock input. It has no
undefined states or race condition, however. It is always edge triggered;
normally on the falling edge.
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